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Systems Engineering

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We have witnessed a big paradigm shift in how AI has affected our daily lives. While AI model training is typically done in a cloud infrastructure setting, model inferencing has grown enormously on power, area, bandwidth and memory constrained edge devices.

These inferencing workloads have varying computational and memory needs, stringent power and silicon area requirements that can be very challenging to meet. AI led innovation is affecting the next generation of embedded hardware and software design alike. This talk will illustrate the design philosophies and challenges around designing best in class AI hardware accelerators.

 

Chip Design
Novel AI Hardware
Hardware Engineering
Strategy
Systems Engineering

Author:

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems
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Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

In developing applications for a variety of different infrastructure and hardware targets, machine learning developers face a dynamic and uncertain landscape where optimization and interoperability become challenging tasks. 

This panel will address how to build infrastructure with developer efficiency in mind, so that developers can focus on creating game-changing machine learning solutions for organizations and consumers. It will also address how hardware, systems and other technology vendors can assist in this effort.

Developer Efficiency
Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

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Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

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Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Sree Ganesan

VP of Product
d-Matrix

Sree Ganesan, VP of Product, d-Matrix: Sree is responsible for product management functions and business development efforts across the company. She manages the product lifecycle, definition and translation of customer needs to the product development function, acting as the voice of the customer. Prior, Sree led the Software Product Management effort at Habana Labs/Intel, delivering state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators. Sree earned a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras and a PhD in computer engineering from the University of Cincinnati, Ohio.

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Sree Ganesan

VP of Product
d-Matrix

Sree Ganesan, VP of Product, d-Matrix: Sree is responsible for product management functions and business development efforts across the company. She manages the product lifecycle, definition and translation of customer needs to the product development function, acting as the voice of the customer. Prior, Sree led the Software Product Management effort at Habana Labs/Intel, delivering state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators. Sree earned a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras and a PhD in computer engineering from the University of Cincinnati, Ohio.

Author:

Daniel Wu

Strategic AI Leadership | Keynote Speaker | Educator | Entrepreneur Course Facilitator
Stanford University AI Professional Program

Daniel Wu is an accomplished technical leader with over 20 years of expertise in software engineering, AI/ML, and team development. With a diverse career spanning technology, education, finance, and healthcare, he is credited for establishing high-performing AI teams, pioneering point-of-care expert systems, co-founding a successful online personal finance marketplace, and leading the development of an innovative online real estate brokerage platform. Passionate about technology democratization and ethical AI practices, Daniel actively promotes these principles through involvement in computer science and AI/ML education programs. A sought-after speaker, he shares insights and experiences at international conferences and corporate events. Daniel holds a computer science degree from Stanford University.

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Daniel Wu

Strategic AI Leadership | Keynote Speaker | Educator | Entrepreneur Course Facilitator
Stanford University AI Professional Program

Daniel Wu is an accomplished technical leader with over 20 years of expertise in software engineering, AI/ML, and team development. With a diverse career spanning technology, education, finance, and healthcare, he is credited for establishing high-performing AI teams, pioneering point-of-care expert systems, co-founding a successful online personal finance marketplace, and leading the development of an innovative online real estate brokerage platform. Passionate about technology democratization and ethical AI practices, Daniel actively promotes these principles through involvement in computer science and AI/ML education programs. A sought-after speaker, he shares insights and experiences at international conferences and corporate events. Daniel holds a computer science degree from Stanford University.

 

Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering
Hardware Engineering

Author:

Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

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Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

 

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Mark Russinovich

CTO and Technical Fellow, Azure
Microsoft

Mark Russinovich is Chief Technology Officer and Technical Fellow for Microsoft Azure, Microsoft’s global enterprise-grade cloud platform. A widely recognized expert in distributed systems, operating systems and cybersecurity, Mark earned a Ph.D. in computer engineering from Carnegie Mellon University. He later co-founded Winternals Software, joining Microsoft in 2006 when the company was acquired. Mark is a popular speaker at industry conferences such as Microsoft Ignite, Microsoft Build, and RSA Conference. He has authored several nonfiction and fiction books, including the Microsoft Press Windows Internals book series, Troubleshooting with the Sysinternals Tools, as well as fictional cyber security thrillers Zero Day, Trojan Horse and Rogue Code.

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Mark Russinovich

CTO and Technical Fellow, Azure
Microsoft

Mark Russinovich is Chief Technology Officer and Technical Fellow for Microsoft Azure, Microsoft’s global enterprise-grade cloud platform. A widely recognized expert in distributed systems, operating systems and cybersecurity, Mark earned a Ph.D. in computer engineering from Carnegie Mellon University. He later co-founded Winternals Software, joining Microsoft in 2006 when the company was acquired. Mark is a popular speaker at industry conferences such as Microsoft Ignite, Microsoft Build, and RSA Conference. He has authored several nonfiction and fiction books, including the Microsoft Press Windows Internals book series, Troubleshooting with the Sysinternals Tools, as well as fictional cyber security thrillers Zero Day, Trojan Horse and Rogue Code.

Chip Design
Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents

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Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents

Macrotrends in innovation are leveraging both software and chips to create the next round of world-changing products. Unlocking the vast potential offered by this innovation model is daunting however. Systemic complexity across all disciplines from silicon to software must be addressed in a holistic way to achieve success. AI applications change over months while chip design can take years, adding to the challenges. Talent shortages also create headwinds. And as more system companies engage in chip design, these headwinds can have a profound impact on the pace of innovation.

Complex chip and system design must be easier to achieve in less time. Sassine Ghazi will discuss several developing strategies that use AI and machine learning techniques to dramatically reduce design time and design risk, opening the opportunity for substantial increases in the pace of innovation.

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering
Systems Engineering

Author:

Sassine Ghazi

CEO
Synopsys

Sassine Ghazi leads and drives strategy for all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. He joined the company in 1998 as an applications engineer. He then held a series of sales positions with increasing responsibility, culminating in leadership of worldwide strategic accounts. He was then appointed general manager for all digital and custom products, the largest business group in Synopsys. Under his leadership, several innovative solutions were launched in areas such as multi-die systems, AI-assisted design and silicon lifecycle management. He assumed the role of chief operating officer in August, 2020 and was appointed to the role of president in November 2021. Prior to Synopsys he was a design engineer at Intel.

 

Sassine holds a bachelor’s degree in Business Administration from Lebanese American University; a B.S.E.E from the Georgia Institute of Technology and an M.S.E.E. from the University of Tennessee.

 

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Sassine Ghazi

CEO
Synopsys

Sassine Ghazi leads and drives strategy for all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. He joined the company in 1998 as an applications engineer. He then held a series of sales positions with increasing responsibility, culminating in leadership of worldwide strategic accounts. He was then appointed general manager for all digital and custom products, the largest business group in Synopsys. Under his leadership, several innovative solutions were launched in areas such as multi-die systems, AI-assisted design and silicon lifecycle management. He assumed the role of chief operating officer in August, 2020 and was appointed to the role of president in November 2021. Prior to Synopsys he was a design engineer at Intel.

 

Sassine holds a bachelor’s degree in Business Administration from Lebanese American University; a B.S.E.E from the Georgia Institute of Technology and an M.S.E.E. from the University of Tennessee.

 

Many system companies are discovering that optimizing AI/ML SoC devices is a very powerful way to achieve differentiation for specific end-applications. In 2021 the semiconductor industry experienced more rounds of venture capital funding and dollars invested than ever before. What’s more, the investments in new AI companies alonewere higher than all prior yearly totals for all design types combined. Most of these new semiconductor companies targeted specific use cases of AI/ML to achieve aggressive performance, power/heat and other system objectives. Now, system companies are designing their own custom AI/ML SoCs—whether it is hyperscalers, automotive OEMs, edge or telecommunication companies–to address their own unique system-level needs.

Joe Sawicki, executive vice president, IC Siemens EDA, will explain how SoC design solutions are enabling both semiconductor and system companies to efficiently arrive at the global optimization point between power, performance, cost, yield and other factors in their AI/ML hardware designs.  All focused on achieving a holistic, optimized system-level differentiation.

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering
Systems Engineering

Author:

Joseph Sawicki

EVP, IC EDA
Siemens

Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.

 

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Joseph Sawicki

EVP, IC EDA
Siemens

Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.

 

Developer Efficiency
Enterprise AI
Data Science
Software Engineering
Systems Engineering
Moderator

Author:

Carlos Guestrin

Professor, Computer Science
Stanford

Carlos Guestrin is a Professor in the Computer Science Department at Stanford University. His previous positions include the Amazon Professor of Machine Learning at the Computer Science & Engineering Department of the University of Washington, the Finmeccanica Associate Professor at Carnegie Mellon University, and the Senior Director of Machine Learning and AI at Apple, after the acquisition of Turi, Inc. (formerly GraphLab and Dato) — Carlos co-founded Turi, which developed a platform for developers and data scientist to build and deploy intelligent applications. He is a technical advisor for OctoML.ai. His team also released a number of popular open-source projects, including XGBoost, LIME, Apache TVM, MXNet, Turi Create, GraphLab/PowerGraph, SFrame, and GraphChi. Carlos received the IJCAI Computers and Thought Award and the Presidential Early Career Award for Scientists and Engineers (PECASE). He is also a recipient of the ONR Young Investigator Award, NSF Career Award, Alfred P. Sloan Fellowship, and IBM Faculty Fellowship, and was named one of the 2008 ‘Brilliant 10’ by Popular Science Magazine. Carlos’ work received awards at a number of conferences and journals, including ACL, AISTATS, ICML, IPSN, JAIR, JWRPM, KDD, NeurIPS, UAI, and VLDB. He is a former member of the Information Sciences and Technology (ISAT) advisory group for DARPA.

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Carlos Guestrin

Professor, Computer Science
Stanford

Carlos Guestrin is a Professor in the Computer Science Department at Stanford University. His previous positions include the Amazon Professor of Machine Learning at the Computer Science & Engineering Department of the University of Washington, the Finmeccanica Associate Professor at Carnegie Mellon University, and the Senior Director of Machine Learning and AI at Apple, after the acquisition of Turi, Inc. (formerly GraphLab and Dato) — Carlos co-founded Turi, which developed a platform for developers and data scientist to build and deploy intelligent applications. He is a technical advisor for OctoML.ai. His team also released a number of popular open-source projects, including XGBoost, LIME, Apache TVM, MXNet, Turi Create, GraphLab/PowerGraph, SFrame, and GraphChi. Carlos received the IJCAI Computers and Thought Award and the Presidential Early Career Award for Scientists and Engineers (PECASE). He is also a recipient of the ONR Young Investigator Award, NSF Career Award, Alfred P. Sloan Fellowship, and IBM Faculty Fellowship, and was named one of the 2008 ‘Brilliant 10’ by Popular Science Magazine. Carlos’ work received awards at a number of conferences and journals, including ACL, AISTATS, ICML, IPSN, JAIR, JWRPM, KDD, NeurIPS, UAI, and VLDB. He is a former member of the Information Sciences and Technology (ISAT) advisory group for DARPA.

Author:

Sakyasingha Dasgupta

Founder & CEO
EdgeCortix

Sakya is the founder and Chief Executive officer of EdgeCortix. He is an artificial intelligence (AI) and machine learning technologist, entrepreneur, and engineer with over a decade of experience in taking cutting edge AI research from ideation stage to scalable products, across different industry verticals.  He has lead teams at global companies like Microsoft and IBM Research / IBM Japan, along with national research labs like RIKEN Japan and the Max Planck Institute Germany. Previously, he helped establish and lead the technology division at lean startups in Japan and Singapore, in semiconductor technology, robotics and Fintech sectors. Sakya is the inventor of over 20 patents and has published widely on machine learning and AI with over 1,000 citations. 

Sakya holds a PhD. in Physics of Complex Systems from the Max Planck Institute in Germany, along with Masters in Artificial Intelligence from The University of Edinburgh and a Bachelors of Computer Engineering. Prior to founding EdgeCortix he completed his entrepreneurship studies from the MIT Sloan School of Management.

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Sakyasingha Dasgupta

Founder & CEO
EdgeCortix

Sakya is the founder and Chief Executive officer of EdgeCortix. He is an artificial intelligence (AI) and machine learning technologist, entrepreneur, and engineer with over a decade of experience in taking cutting edge AI research from ideation stage to scalable products, across different industry verticals.  He has lead teams at global companies like Microsoft and IBM Research / IBM Japan, along with national research labs like RIKEN Japan and the Max Planck Institute Germany. Previously, he helped establish and lead the technology division at lean startups in Japan and Singapore, in semiconductor technology, robotics and Fintech sectors. Sakya is the inventor of over 20 patents and has published widely on machine learning and AI with over 1,000 citations. 

Sakya holds a PhD. in Physics of Complex Systems from the Max Planck Institute in Germany, along with Masters in Artificial Intelligence from The University of Edinburgh and a Bachelors of Computer Engineering. Prior to founding EdgeCortix he completed his entrepreneurship studies from the MIT Sloan School of Management.

Author:

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design. He is a recipient of an NSF CAREER Award, a Sloan Research Fellowship, a Microsoft Research Faculty Fellowship, the IEEE TCCA young Computer Architect Award and UIUC Distinguished Alumni Award.

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Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design. He is a recipient of an NSF CAREER Award, a Sloan Research Fellowship, a Microsoft Research Faculty Fellowship, the IEEE TCCA young Computer Architect Award and UIUC Distinguished Alumni Award.

Author:

Jian Zhang

Director, Machine Learning
SambaNova Systems
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Jian Zhang

Director, Machine Learning
SambaNova Systems

Transformers are in high demand, particularly in industries like BFSI and healthcare, for language processing, understanding, classification, generation and translation. The parameter counts for models like GPT, that are fast becoming the norm in the world of NLP, are mind-boggling, and the cost involved in training and deploying even more so. If the vast potential for LLMs is to extend beyond the wealthiest companies and research institutions on the planet, then there is a need to evaluate how to lower the barriers of entry for experimentation and research on models like GPT. There's also a need to discuss the extent to which bigger is better, in the field of practical and commercial NLP.

This panel will look at the state of play of how enterprises are using large language models today, what their plans are for future research in NLP, and how hardware & systems builders and organizations like HuggingFace can help bring state-of-the-art performance into production in smaller, more resource-constrained enterprises and labs.

Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

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Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

Author:

Selcuk Kopru

Director, Engineering & Research, Search
eBay

Selcuk Kopru is Head of ML & NLP at eBay and is an experienced AI leader with proven expertise in creating and deploying cutting edge NLP and AI technologies and systems. He is experienced in developing scalable Machine Learning solutions to solve big data problems that involve text and multimodal data. He is also skilled in Python, Java, C++, Machine Translation and Pattern Recognition. Selcuk is also a strong research professional with a Doctor of Philosophy (PhD) in NLP in Computer Science from Middle East Technical University.

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Selcuk Kopru

Director, Engineering & Research, Search
eBay

Selcuk Kopru is Head of ML & NLP at eBay and is an experienced AI leader with proven expertise in creating and deploying cutting edge NLP and AI technologies and systems. He is experienced in developing scalable Machine Learning solutions to solve big data problems that involve text and multimodal data. He is also skilled in Python, Java, C++, Machine Translation and Pattern Recognition. Selcuk is also a strong research professional with a Doctor of Philosophy (PhD) in NLP in Computer Science from Middle East Technical University.

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Morteza Noshad

Senior ML/NLP Scientist
Vida Health

Morteza Noshad is a senior ML/NLP scientist at Vida health. He is skilled at designing large scale NLP models for different healthcare applications such as automated clinical documentation, symptom detection and question answering. Morteza was a research scientist at Stanford University focusing on graph neural networks for clinical decision support systems where he received the SAGE Scientist Award for his research. Morteza received his Ph.D. in Computer Science from University of Michigan where he contributed to the theory of information bottleneck in deep learning. 

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Morteza Noshad

Senior ML/NLP Scientist
Vida Health

Morteza Noshad is a senior ML/NLP scientist at Vida health. He is skilled at designing large scale NLP models for different healthcare applications such as automated clinical documentation, symptom detection and question answering. Morteza was a research scientist at Stanford University focusing on graph neural networks for clinical decision support systems where he received the SAGE Scientist Award for his research. Morteza received his Ph.D. in Computer Science from University of Michigan where he contributed to the theory of information bottleneck in deep learning. 

AI acceleration is a full stack effort and involves a multidisciplinary and holistic approach to design and optimization.

The field of deep learning has gained substantially from co-design concepts across the AI technology stack. The simultaneous design and optimization of hardware and software has led to new algorithms, numerical optimizations, and AI hardware. 

Looking at the AI stack for workloads like computer vision, NLP and Ads, in both a vertical and horizontal sense, there are significant opportunities and challenges for optimization through co-design. This panel will focus on software-defined chips and systems for AI (specs & evaluation, datacenter & edge) and look at the systems-level approach to co-design, including compilers and runtime etc.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Nick Ni

Senior Director, Datacenter AI & Compute Markets
AMD

Nick Ni is Senior Director, Data Center AI and Compute Markets at Adaptive Embedded Computing Group (AECG) at AMD, responsible for the P&L of the fast-growing Data Center AI and compute segment. His team is responsible for product marketing and product management including AI product planning, go-to-market, business development and solution architecture.

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Nick Ni

Senior Director, Datacenter AI & Compute Markets
AMD

Nick Ni is Senior Director, Data Center AI and Compute Markets at Adaptive Embedded Computing Group (AECG) at AMD, responsible for the P&L of the fast-growing Data Center AI and compute segment. His team is responsible for product marketing and product management including AI product planning, go-to-market, business development and solution architecture.

Author:

Xiaoyong Liu

Director, AI Platform
Alibaba
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Xiaoyong Liu

Director, AI Platform
Alibaba

Author:

Shubho Sengupta

Software Engineer
Meta

Shubho Sengupta is a Software Engineer at Meta, where he designs Meta’s Research Infra for AI training. He started working on AI in 2014, on speech related AI models like DeepSpeech and DeepVoice. Before that he pioneered many of the foundational algorithms in general purpose programming in GPUs, which has won Test of Time award. These days, he also works at the intersection of cryptography and computation, specifically in bi-partite and multi-partite matching algorithms.

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Shubho Sengupta

Software Engineer
Meta

Shubho Sengupta is a Software Engineer at Meta, where he designs Meta’s Research Infra for AI training. He started working on AI in 2014, on speech related AI models like DeepSpeech and DeepVoice. Before that he pioneered many of the foundational algorithms in general purpose programming in GPUs, which has won Test of Time award. These days, he also works at the intersection of cryptography and computation, specifically in bi-partite and multi-partite matching algorithms.

Author:

Dr. Charles Fan

CEO and Co-Founder
MemVerge

Charles Fan is CEO and co-founder of MemVerge. Prior to MemVerge, Charles was the CTO of Cheetah Mobile leading its global technology teams, and an SVP/GM at VMware, founding the storage business unit that developed the Virtual SAN product. Charles also worked at EMC and was the founder of the EMC China R&D Center. Charles joined EMC via the acquisition of Rainfinity, where he was a co-founder and CTO. Charles received his Ph.D. and M.S. in Electrical Engineering from the California Institute of Technology, and his B.E. in Electrical Engineering from the Cooper Union.

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Dr. Charles Fan

CEO and Co-Founder
MemVerge

Charles Fan is CEO and co-founder of MemVerge. Prior to MemVerge, Charles was the CTO of Cheetah Mobile leading its global technology teams, and an SVP/GM at VMware, founding the storage business unit that developed the Virtual SAN product. Charles also worked at EMC and was the founder of the EMC China R&D Center. Charles joined EMC via the acquisition of Rainfinity, where he was a co-founder and CTO. Charles received his Ph.D. and M.S. in Electrical Engineering from the California Institute of Technology, and his B.E. in Electrical Engineering from the Cooper Union.

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Zaid Kahn

VP, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently a VP in Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering organization where he leads systems engineering and hardware development for Azure including AI systems and infrastructure. Zaid is part of the technical leadership team across Microsoft that sets AI hardware strategy for training and inference. Zaid's teams are also responsible for software and hardware engineering efforts developing specialized compute systems, FPGA network products and ASIC hardware accelerators.

 

Prior to Microsoft Zaid was head of infrastructure at LinkedIn where he was responsible for all aspects of architecture and engineering for Datacenters, Networking, Compute, Storage and Hardware. Zaid also led several software development teams focusing on building and managing infrastructure as code. This included zero touch provisioning, software-defined networking, network operating systems (SONiC, OpenSwitch), self-healing networks, backbone controller, software defined storage and distributed host-based firewalls. The network teams Zaid led built the global network for LinkedIn, including POP's, peering for edge services, IPv6 implementation, DWDM infrastructure and datacenter network fabric. The hardware and datacenter engineering teams Zaid led were responsible for water cooling to the racks, optical fiber infrastructure and open hardware development which was contributed to the Open Compute Project Foundation (OCP).

 

Zaid holds several patents in networking and is a sought-after keynote speaker at top tier conferences and events. Zaid is currently the chairperson for the OCP Foundation Board. He is also currently on the EECS External Advisory Board (EAB) at UC Berkeley and a board member of Internet Ecosystem Innovation Committee (IEIC), a global internet think tank promoting internet diversity. Zaid has a Bachelor of Science in Computer Science and Physics from the University of the South Pacific.

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Zaid Kahn

VP, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently a VP in Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering organization where he leads systems engineering and hardware development for Azure including AI systems and infrastructure. Zaid is part of the technical leadership team across Microsoft that sets AI hardware strategy for training and inference. Zaid's teams are also responsible for software and hardware engineering efforts developing specialized compute systems, FPGA network products and ASIC hardware accelerators.

 

Prior to Microsoft Zaid was head of infrastructure at LinkedIn where he was responsible for all aspects of architecture and engineering for Datacenters, Networking, Compute, Storage and Hardware. Zaid also led several software development teams focusing on building and managing infrastructure as code. This included zero touch provisioning, software-defined networking, network operating systems (SONiC, OpenSwitch), self-healing networks, backbone controller, software defined storage and distributed host-based firewalls. The network teams Zaid led built the global network for LinkedIn, including POP's, peering for edge services, IPv6 implementation, DWDM infrastructure and datacenter network fabric. The hardware and datacenter engineering teams Zaid led were responsible for water cooling to the racks, optical fiber infrastructure and open hardware development which was contributed to the Open Compute Project Foundation (OCP).

 

Zaid holds several patents in networking and is a sought-after keynote speaker at top tier conferences and events. Zaid is currently the chairperson for the OCP Foundation Board. He is also currently on the EECS External Advisory Board (EAB) at UC Berkeley and a board member of Internet Ecosystem Innovation Committee (IEIC), a global internet think tank promoting internet diversity. Zaid has a Bachelor of Science in Computer Science and Physics from the University of the South Pacific.